Field of the Invention
The present invention relates to a data processing device and a data transfer control device.
Priority is claimed on Japanese Patent Application No. 2013-121935, filed Jun. 10, 2013, the contents of which are incorporated herein by reference.
Description of Related Art
In a large number of system LSIs, including a system LSI mounted on an image processing device such as a camera for still images, a camera for moving images, a medical endoscope camera or an industrial endoscope camera, a plurality of embedded processing blocks share one connected DRAM (Dynamic Random Access Memory). In such a system LSI, the plurality of embedded processing blocks are connected to a data bus in the system LSI, and each processing block performs access to the DRAM through DMA (Direct Memory Access). In this case, a bus arbiter controls the access to the DRAM while appropriately arbitrating requests for access (DMA requests) to the DRAM generated from the respective processing blocks.
A method called bank interleave is used to secure a bus band of the entire data bus at the time of access to a general DRAM. Here, the bus band indicates an amount of data on the data bus when each processing block accesses the DRAM. In the bank interleave, data transfer is controlled for each bank of the DRAM. When sequential access to different banks of the DRAM is performed through bank interleave, a process of setting an address of a bank to be accessed next during a process of data transfer from a first accessed bank can be performed in parallel. Therefore, it is possible to improve the efficiency of data access to the DRAM.
However, there is a period in which access cannot be accepted when the same bank is continuously accessed in the DRAM. Therefore, when the same bank of the DRAM is continuously accessed through bank interleave, loss time is generated due to the period in which the DRAM cannot accept the access, and the efficiency of data access to the DRAM is degraded. Therefore, it is necessary to sequentially access different banks through the bank interleave in order to secure high efficiency of data access by performing a data transfer process and an address setting process in parallel.
A method of preferentially accepting an access request from a processing block having high priority based on priorities of respective processing blocks in arbitration of access requests to DRAM in a general bus arbiter is known. Such a method may include, for example, a processing block in which processing breaks down when access to the DRAM is obstructed for a certain period of time. A method of securing a bus band of the entire data bus by selecting a processing block whose access request is accepted based on information of banks to be accessed is known. Such a method may include, for example, lowering priority of continuous access to the same bank.
However, when a system becomes complicated, the number of processing blocks embedded in the system LSI increases. Accordingly, a setting of priority for the respective processing blocks becomes complicated, and it is difficult to appropriately arbitrate requests for access to the DRAM from the processing blocks using only a bus arbiter.
A technology used to secure performance of a system by improving the bus band of the entire data bus through bank interleave, that is, improving the efficiency of data access to a DRAM while securing the bus band required by each processing block in order to solve such a problem, is conventionally disclosed.
A technology disclosed in Japanese Unexamined Patent Application, First Publication No. 2011-3160 is a technology used to perform control so that a processing block having high priority continuously accesses different banks of a DRAM by controlling the timing at which each processing block generates a request to access to the DRAM (request generation timing) or a method of generating addresses of the DRAM to be accessed by each processing block. According to this technology, it is possible to secure the bus band of the entire data bus while securing the priority of each processing block, that is, to efficiently perform data transfer.
A technology disclosed in Japanese Unexamined Patent Application, First Publication No. 2006-260472 or Japanese Unexamined Patent Application, First Publication No. 2010-27006 is a technology used to prevent continuous access to the same bank of a DRAM by changing, within a bus arbiter, the order that each bank accesses to the DRAM. According to this technology, generation of loss time in which the DRAM cannot accept the access can be minimized.
In recent years, with increasing of the speed of image processing devices, the speed of image sensors mounted on image processing devices have also been increasing. For example, an image sensor with a high speed by simultaneously outputting signals of a plurality of pixels is shown in Japanese Unexamined Patent Application, First Publication No. 2008-5048. Output forms of an imager which simultaneously outputs a plurality of pixel signals include, for example, a form of simultaneously outputting pixel signals of two pixels adjacent in a horizontal direction, and a form of simultaneously outputting pixel signals of two pixels adjacent in a vertical direction. In addition, in Japanese Unexamined Patent Application, First Publication No. 2008-5048, as an image sensor which is provided with two output channels which output signals of pixels, an image sensor, which outputs a signal of pixels of odd-numbered lines and even-numbered lines in a horizontal direction, and an image sensor, which outputs a signal of pixels of odd-numbered lines and even-numbered lines in a vertical direction, are disclosed.